問題一覧
1
PUT
2
UCSZ0
3
Virtual relay contacts and coils
4
Address bus, data bus, control bus
5
Byte is assigned an I/O address.
6
Coincide with the poles
7
Xc = R at the cutoff frequency.
8
using Boolean algebra
9
the way we OR or AND two variables is unimportant because the result is the same
10
Gate, anode 1, and anode 2.
11
3 terminal, self-controlled device
12
As a system parameter is changed.
13
4 to 16 lines
14
No oscillation
15
8
16
DRAM - Dynamic Random-Access Memory.
17
mount directly
18
Zero to 0.8 volts.
19
gate, anode, cathode
20
7400 has four two-input NAND gates; 7411 has three three-input AND gates
21
PSW
22
programmable interval timer
23
The interrupt that is more priority in the interrupt vector table will be served first.
24
Requirement of system recalibration from time to time
25
-2
26
All of the mentioned
27
isolation transformer
28
A high-logic state.
29
12.0 V
30
No change
31
0.65
32
Ex-OR gate
33
falls below the latching current
34
CPU, RAM, I/O ports, and timers
35
the diode should be replaced by a diac
36
High level.
37
an integrator circuit
38
p-i-n photoreceiver
39
negative pulse to the anode gate, positive pulse to the cathode gate
40
p+ n+ diode with p+ electrodes
41
both line and natural commutation
42
multiple, multiple
43
To generate a direct current
44
Pi-L network
45
Propagation delay
46
SUS
47
Assembler
48
Numerical controlled machines
49
CPU off
50
a diode in anti-parallel with the SCR
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100問 • 1年前問題一覧
1
PUT
2
UCSZ0
3
Virtual relay contacts and coils
4
Address bus, data bus, control bus
5
Byte is assigned an I/O address.
6
Coincide with the poles
7
Xc = R at the cutoff frequency.
8
using Boolean algebra
9
the way we OR or AND two variables is unimportant because the result is the same
10
Gate, anode 1, and anode 2.
11
3 terminal, self-controlled device
12
As a system parameter is changed.
13
4 to 16 lines
14
No oscillation
15
8
16
DRAM - Dynamic Random-Access Memory.
17
mount directly
18
Zero to 0.8 volts.
19
gate, anode, cathode
20
7400 has four two-input NAND gates; 7411 has three three-input AND gates
21
PSW
22
programmable interval timer
23
The interrupt that is more priority in the interrupt vector table will be served first.
24
Requirement of system recalibration from time to time
25
-2
26
All of the mentioned
27
isolation transformer
28
A high-logic state.
29
12.0 V
30
No change
31
0.65
32
Ex-OR gate
33
falls below the latching current
34
CPU, RAM, I/O ports, and timers
35
the diode should be replaced by a diac
36
High level.
37
an integrator circuit
38
p-i-n photoreceiver
39
negative pulse to the anode gate, positive pulse to the cathode gate
40
p+ n+ diode with p+ electrodes
41
both line and natural commutation
42
multiple, multiple
43
To generate a direct current
44
Pi-L network
45
Propagation delay
46
SUS
47
Assembler
48
Numerical controlled machines
49
CPU off
50
a diode in anti-parallel with the SCR