ELEX 2
問題一覧
1
to ensure proper voltage division
2
False
3
By connecting a radio frequency capacitor from Vcc to ground
4
False
5
MOSFET
6
Gate Triggering
7
unused input that is not connected.
8
a capacitor and a auto transformer
9
AS-TTL
10
Aluminum
11
The input gates of the FETs are predominantly capacitive, and as the signal frequency increases, thereby limiting the number of loads that may he attached to the output of the driving gate.
12
Shockly Diode
13
holes, electrons
14
Silicon
15
Parallel resonant frequency is approximately 1 kHz higher than series resonant frequency.
16
29
17
Hartley oscillator
18
varies between maximum and minimum values
19
decreases
20
is constant in reverse direction
21
maximum
22
minimum
23
Hartley
24
may be any type of load
25
emitter-coupled logic (ECL) and transistor-transistor logic (TTL)
26
Ton/(Ton + Toff)
27
Vdc Idc/(Vs Is)
28
All of the above
29
2
30
high, low
31
Trigger Current
32
difference
33
the maximum rate of rise of anode voltage which will not trigger the SCR if gate signal is applied.
34
4 semiconductor layers and 3 junctions.
35
Thyristor
36
positive feedback greater than 1
37
80% or more
38
one converter is always working as rectifier and other as inverter.
39
forward, forward
40
All of the above
41
B = a/(1 - a)
42
1 + BA
43
two 3 phase full converters connected in antiparallel
44
4
45
Fundamental
46
a Schottky diode has lower cut in voltage wnd higher reverse current
47
rectangular
48
All of the above
49
application of positive pulse at cathode gate or negative pulse at anode gate.
50
Complementary Commutation
51
much larger than
52
two junction are reverse biased and one junction is forward biased
53
3, 1, 2
54
very high, very small
55
1
56
appears across only one junction
57
True
58
base current Ib
59
10
60
Antimony
61
3, 2, 3
62
the distortion of output voltage waveform is high
63
Class A chopper operates in first quadrant and Class B chopper operates in second quadrant
64
SCR is clamped between two disc shaped heat sink
65
0°
66
ECL
67
reverse bias
68
A larger value resistor
69
True
70
the waveshape of output voltage is square but the waveshape of load current is nearly sinusoidal.
71
Evanescent Wave
72
Both A and the phase shift between input and output signals.
73
immobile charges
74
Self Commutation
75
2
76
more than that in germanium
77
50 to 300, less than 1
78
True
79
HVDC transmission, electrical isolation
80
bandstop
81
decrease the output voltage
82
20,000
83
As long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
84
Holes exist in conductors as well as semiconductors.
85
3, 3, 4
86
1
87
AS-TTL
88
the output frequency can be even higher than the frequency of damped oscillation.
89
reducing the switching time
90
µA, mA
91
2
92
is always positive
93
when anode current becomes zero.
94
25 to 500
95
False
96
Greater than -29
97
4 thyristors
98
The 5409 series are military grade and allow for a wider range of supply voltages and temperatures.
99
Both BA > 1 and the phase shift around the feedback network must be 180°.
100
Colpitts
Basic Communication I
Basic Communication I
John Cerda · 100問 · 2年前Basic Communication I
Basic Communication I
100問 • 2年前Basic Communication II
Basic Communication II
John Cerda · 100問 · 2年前Basic Communication II
Basic Communication II
100問 • 2年前Basic Communication III
Basic Communication III
John Cerda · 50問 · 2年前Basic Communication III
Basic Communication III
50問 • 2年前Amplitude Modulation I
Amplitude Modulation I
John Cerda · 100問 · 2年前Amplitude Modulation I
Amplitude Modulation I
100問 • 2年前Amplitude Modulation II
Amplitude Modulation II
John Cerda · 100問 · 2年前Amplitude Modulation II
Amplitude Modulation II
100問 • 2年前Angle Modulation I
Angle Modulation I
John Cerda · 100問 · 2年前Angle Modulation I
Angle Modulation I
100問 • 2年前Angle Modulation II
Angle Modulation II
John Cerda · 58問 · 2年前Angle Modulation II
Angle Modulation II
58問 • 2年前Transmission Line I
Transmission Line I
John Cerda · 100問 · 2年前Transmission Line I
Transmission Line I
100問 • 2年前Transmission Line II
Transmission Line II
John Cerda · 37問 · 2年前Transmission Line II
Transmission Line II
37問 • 2年前Differential Calculus
Differential Calculus
John Cerda · 84問 · 2年前Differential Calculus
Differential Calculus
84問 • 2年前Integral Calculus
Integral Calculus
John Cerda · 53問 · 2年前Integral Calculus
Integral Calculus
53問 • 2年前DC Circuit
DC Circuit
John Cerda · 63問 · 2年前DC Circuit
DC Circuit
63問 • 2年前Differential Equation
Differential Equation
John Cerda · 21問 · 2年前Differential Equation
Differential Equation
21問 • 2年前ELEX 3
ELEX 3
John Cerda · 100問 · 2年前ELEX 3
ELEX 3
100問 • 2年前ELEX 4
ELEX 4
John Cerda · 100問 · 2年前ELEX 4
ELEX 4
100問 • 2年前ELEX 5
ELEX 5
John Cerda · 59問 · 2年前ELEX 5
ELEX 5
59問 • 2年前MATH
MATH
John Cerda · 78問 · 2年前MATH
MATH
78問 • 2年前問題一覧
1
to ensure proper voltage division
2
False
3
By connecting a radio frequency capacitor from Vcc to ground
4
False
5
MOSFET
6
Gate Triggering
7
unused input that is not connected.
8
a capacitor and a auto transformer
9
AS-TTL
10
Aluminum
11
The input gates of the FETs are predominantly capacitive, and as the signal frequency increases, thereby limiting the number of loads that may he attached to the output of the driving gate.
12
Shockly Diode
13
holes, electrons
14
Silicon
15
Parallel resonant frequency is approximately 1 kHz higher than series resonant frequency.
16
29
17
Hartley oscillator
18
varies between maximum and minimum values
19
decreases
20
is constant in reverse direction
21
maximum
22
minimum
23
Hartley
24
may be any type of load
25
emitter-coupled logic (ECL) and transistor-transistor logic (TTL)
26
Ton/(Ton + Toff)
27
Vdc Idc/(Vs Is)
28
All of the above
29
2
30
high, low
31
Trigger Current
32
difference
33
the maximum rate of rise of anode voltage which will not trigger the SCR if gate signal is applied.
34
4 semiconductor layers and 3 junctions.
35
Thyristor
36
positive feedback greater than 1
37
80% or more
38
one converter is always working as rectifier and other as inverter.
39
forward, forward
40
All of the above
41
B = a/(1 - a)
42
1 + BA
43
two 3 phase full converters connected in antiparallel
44
4
45
Fundamental
46
a Schottky diode has lower cut in voltage wnd higher reverse current
47
rectangular
48
All of the above
49
application of positive pulse at cathode gate or negative pulse at anode gate.
50
Complementary Commutation
51
much larger than
52
two junction are reverse biased and one junction is forward biased
53
3, 1, 2
54
very high, very small
55
1
56
appears across only one junction
57
True
58
base current Ib
59
10
60
Antimony
61
3, 2, 3
62
the distortion of output voltage waveform is high
63
Class A chopper operates in first quadrant and Class B chopper operates in second quadrant
64
SCR is clamped between two disc shaped heat sink
65
0°
66
ECL
67
reverse bias
68
A larger value resistor
69
True
70
the waveshape of output voltage is square but the waveshape of load current is nearly sinusoidal.
71
Evanescent Wave
72
Both A and the phase shift between input and output signals.
73
immobile charges
74
Self Commutation
75
2
76
more than that in germanium
77
50 to 300, less than 1
78
True
79
HVDC transmission, electrical isolation
80
bandstop
81
decrease the output voltage
82
20,000
83
As long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
84
Holes exist in conductors as well as semiconductors.
85
3, 3, 4
86
1
87
AS-TTL
88
the output frequency can be even higher than the frequency of damped oscillation.
89
reducing the switching time
90
µA, mA
91
2
92
is always positive
93
when anode current becomes zero.
94
25 to 500
95
False
96
Greater than -29
97
4 thyristors
98
The 5409 series are military grade and allow for a wider range of supply voltages and temperatures.
99
Both BA > 1 and the phase shift around the feedback network must be 180°.
100
Colpitts