Intro to Comp - Lecture 4

34問 • 2年前

問題一覧

For a single-bit full adder circuit, which many input combinations will result in both sum and carry out to be set to 1?

For a half adder circuit, which are the conditions for the sum output to be set to 1?For a half adder circuit, which are the conditions for the sum output to be set to 1?

A=1, B=0, A=0, B=1

Consider the use of multiple single-bit full adder circuits, how many gates will be required to build a 64-bit ripple adder?

320

Indicate the index(row) that is incorrect for the following truth table for a full adder

2, 5

Determine the two entries (highlighted in red) in the truth table of a full adder as shown below.

0 1

List the two missing entries in the truth table for a 2-to-1 multiplexer as shown below. Indicate your answer as (X1 X2) with X1 being the upper entry.

1 0

What is the answer of the following?

3rd option

Which is the correct answer?

4th option

For a 4-bit ripple adder, which pair of inputs will take the longest time to compute?

A=0011 & B=0001

For the implementation of boolean function using multiplexer, where should the input be connected to if the product term is a don't care?

Connect to VDD and GND

Which of the following is correct?

For a 64-to-1 multiplexer, how many select inputs do you expect?

If the data select lines of the MUX are S1S0 = 11, the output will be…

4th option

Given a 4-bit circuit shown below, what is the function of this circuit?

Logical shift right

Express decimal value 24 in 8-bit binary, perform a logically shift 2-bit to the left, what is the answer in decimal?

What is the key limitation to use a shifter circuit to perform arithmetic multiplication (or division)?

Can only perform multiplication (or division) in multiple of 2

For the following circuit, what is the output (expressed in X3X2X1X0) when A3..0 = 0101 and Sh = 0?

1010

Which statement(s) about FPGA and ASIC are correct

ASIC consumes lesser power and occupy less chip area compared to FPGA, FPGA are easily reprogrammable compared to ASIC

How many transistors are required to build a 2-input XOR gate

Which component inside a CPU are synchronous circuit?

Memory, Control Unit

For the following circuit, given fin is 400 MHz, what is the frequency fout?

100MHz

As extracted from the datasheet of a D-type flip flop HCD4013 from ST (www.st.com/resource/en/datasheet/hcf4013.pdf), what does th refers to?

Hold time

When we refer to the state of the art semiconductor manufacturing technology in terms of nanometer (e.g. 5nm) what are we referring to with respect to the transistor?( ans with: ____of the gate)

width

For an SR latch as shown below where S=R=0 and Q=1, what will happen when S is change from 0 to 1 (R remain at 0)

In an active-LOW SR latch, which is the inputs for S and R to change the content of the latch to 1?

S=0 and R=1

How many asynchronous inputs does the J-K flip-flop below have?

As extracted from the datasheet of a D-type flip flop HCD4013 from ST (www.st.com/resource/en/datasheet/hcf4013.pdf), only the minimum and typical data setup time are given. What do you think is the maximum setup time?

Clock period - th

For a D flip-flop with asynchronous active-LOW CLR and PR, what happen to the content Q when the following are asserted: CLR=1 and PR=0?

Q goes to 1

For an SR latch, which signal indicates the content store inside the latch?

The decimal-to-binary encoder shown does not have a zero input. This is because

when zero is the input, all lines should be LOW

S=R=1 is considered a NOT ALLOWED state for an SR latch, what do you think will happen to the SR latch when S and R are set to 1 concurrently

Content cannot be determined

Fo an active-LOW JK flip flop, what happen to its content when both J & K inputs are ‘0’

Content will toggle its state

A comparator circuit is as shown below, what does the output X indicates?

A=B

The D-flip flop shown will _____on the next clock pulse

toggle

1.1: Software life cycle

ユーザ名非公開 · 17問 · 2年前

1.1: Software life cycle