Week 9 Architectures
問題一覧
1
The logical view of a processor as seen by software tools and programmers.
2
Reduced Instruction Set Computer (RISC).
3
To hold the memory address of the next instruction to be executed.
4
Reading the instruction located at the address provided by the PC.
5
To decode the instruction's opcode and generate control signals for other components.
6
The Registers unit (for register numbers) and potentially an adder (for branch offset/immediate values).
7
It is fed to an adder along with the PC value to calculate the branch target address.
8
The calculated branch target address (from the adder) is fed back into the PC.
9
ALU
10
The PC is incremented by one word (usually 4 bytes), as usual for sequential instruction fetching.
1.1: Software life cycle
1.1: Software life cycle
ユーザ名非公開 · 17問 · 2年前1.1: Software life cycle
1.1: Software life cycle
17問 • 2年前Intro to computing - Lecture 1
Intro to computing - Lecture 1
ユーザ名非公開 · 32問 · 2年前Intro to computing - Lecture 1
Intro to computing - Lecture 1
32問 • 2年前Chapter 5
Chapter 5
ユーザ名非公開 · 7問 · 2年前Chapter 5
Chapter 5
7問 • 2年前Intro to Comp - Lecture 4
Intro to Comp - Lecture 4
ユーザ名非公開 · 34問 · 2年前Intro to Comp - Lecture 4
Intro to Comp - Lecture 4
34問 • 2年前Intro to comp - Lecture 3
Intro to comp - Lecture 3
ユーザ名非公開 · 24問 · 2年前Intro to comp - Lecture 3
Intro to comp - Lecture 3
24問 • 2年前Intro to Comp - Lecture 2
Intro to Comp - Lecture 2
ユーザ名非公開 · 28問 · 2年前Intro to Comp - Lecture 2
Intro to Comp - Lecture 2
28問 • 2年前Quiz 2
Quiz 2
ユーザ名非公開 · 7問 · 2年前Quiz 2
Quiz 2
7問 • 2年前1.2: Software Engineering Methodologies
1.2: Software Engineering Methodologies
ユーザ名非公開 · 20問 · 2年前1.2: Software Engineering Methodologies
1.2: Software Engineering Methodologies
20問 • 2年前2.2: Relational Model and ER Model
2.2: Relational Model and ER Model
ユーザ名非公開 · 19問 · 2年前2.2: Relational Model and ER Model
2.2: Relational Model and ER Model
19問 • 2年前2.3: Converting ER Model to Relational model
2.3: Converting ER Model to Relational model
ユーザ名非公開 · 5問 · 2年前2.3: Converting ER Model to Relational model
2.3: Converting ER Model to Relational model
5問 • 2年前Quiz 1
Quiz 1
ユーザ名非公開 · 8問 · 2年前Quiz 1
Quiz 1
8問 • 2年前Week 2 Concurrency
Week 2 Concurrency
ユーザ名非公開 · 10問 · 11ヶ月前Week 2 Concurrency
Week 2 Concurrency
10問 • 11ヶ月前Week 3 Mutual Exclusion
Week 3 Mutual Exclusion
ユーザ名非公開 · 3回閲覧 · 12問 · 11ヶ月前Week 3 Mutual Exclusion
Week 3 Mutual Exclusion
3回閲覧 • 12問 • 11ヶ月前Week 4 Synchronisation
Week 4 Synchronisation
ユーザ名非公開 · 10問 · 11ヶ月前Week 4 Synchronisation
Week 4 Synchronisation
10問 • 11ヶ月前Week 5 Processes and scheduling
Week 5 Processes and scheduling
ユーザ名非公開 · 22問 · 11ヶ月前Week 5 Processes and scheduling
Week 5 Processes and scheduling
22問 • 11ヶ月前Week 6 Interprocess Communication
Week 6 Interprocess Communication
ユーザ名非公開 · 22問 · 11ヶ月前Week 6 Interprocess Communication
Week 6 Interprocess Communication
22問 • 11ヶ月前Week 7 File system
Week 7 File system
ユーザ名非公開 · 13問 · 11ヶ月前Week 7 File system
Week 7 File system
13問 • 11ヶ月前Week 8 Virtual Memory
Week 8 Virtual Memory
ユーザ名非公開 · 22問 · 11ヶ月前Week 8 Virtual Memory
Week 8 Virtual Memory
22問 • 11ヶ月前BigO scenario qns
BigO scenario qns
ユーザ名非公開 · 8問 · 9ヶ月前BigO scenario qns
BigO scenario qns
8問 • 9ヶ月前問題一覧
1
The logical view of a processor as seen by software tools and programmers.
2
Reduced Instruction Set Computer (RISC).
3
To hold the memory address of the next instruction to be executed.
4
Reading the instruction located at the address provided by the PC.
5
To decode the instruction's opcode and generate control signals for other components.
6
The Registers unit (for register numbers) and potentially an adder (for branch offset/immediate values).
7
It is fed to an adder along with the PC value to calculate the branch target address.
8
The calculated branch target address (from the adder) is fed back into the PC.
9
ALU
10
The PC is incremented by one word (usually 4 bytes), as usual for sequential instruction fetching.